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| (R) ISL2100A, ISL2101A Data Sheet June 8, 2006 FN6294.0 100V, 2A Peak, High Frequency Half-Bridge Drivers The ISL2100A, ISL2101A are 100V, high frequency, half-bridge N-channel power MOSFET driver ICs. They are based on the popular HIP2100, HIP2101 half-bridge drivers, but offer several performance improvements. The ISL2100A has additional input hysteresis for superior operation in noisy environments and the inputs of the ISL2101A, like those of the ISL2100A, can now safely swing to the VDD supply rail. Finally, both parts are available in a very compact 9 Ld DFN package to minimize the required PCB footprint. Features * Drives N-Channel MOSFET Half-Bridge * Space-Saving DFN Package * DFN Package Compliant with 100V Conductor Spacing Guidelines per IPC-2221 * Pb-Free Plus Anneal Available (RoHS Compliant) * Bootstrap Supply Max Voltage to 114VDC * On-Chip 1 Bootstrap Diode * Fast Propagation Times for Multi-MHz Circuits * Drives 1nF Load with Typical Rise/Fall Times of 10ns * CMOS Compatible Input Thresholds (ISL2100A) Ordering Information PART NUMBER (Notes 1, 2) PART TEMP. MARKING RANGE (C) -40 to 125 -40 to 125 PACKAGE (Pb-Free) PKG. DWG. # * 3.3V/TTL Compatible Input Thresholds (ISL2101A) * Independent Inputs Provide Flexibility * No Start-Up Problems * Outputs Unaffected by Supply Glitches, HS Ringing Below Ground or HS Slewing at High dv/dt * Low Power Consumption * Wide Supply Voltage Range (9V to 14V) * Supply Undervoltage Protection * 2.5 Typical Output Pull-Up/Pull-Down Resistance ISL2100AAR3Z 00AZ ISL2101AAR3Z 01AZ NOTES: 9 Ld 3x3 DFN L9.3x3 9 Ld 3x3 DFN L9.3x3 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-T" suffix for Tape and Reel packing option. Applications Pinouts ISL2100A, ISL2101A (DFN) TOP VIEW * Telecom Half-Bridge Converters * Telecom Full-Bridge Converters * Two-Switch Forward Converters * Active-Clamp Forward Converters VDD 1 9 LO 8 VSS HB HO HS 2 3 4 EPAD 7 LI 6 HI 5 NC * Class-D Audio Amplifiers NOTE: EPAD = Exposed PAD. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL2100A, ISL2101A Application Block Diagram +12V +100V VDD HB SECONDARY CIRCUIT HI CONTROL PWM CONTROLLER LI DRIVE HI HO HS DRIVE LO ISL2100A ISL2101A VSS LO REFERENCE AND ISOLATION Functional Block Diagram HB VDD UNDER VOLTAGE LEVEL SHIFT DRIVER HS HI ISL2101A HO UNDER VOLTAGE ISL2101A DRIVER LI VSS LO EPAD (DFN Package Only) *EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PCB power ground plane. 2 FN6294.0 June 8, 2006 ISL2100A, ISL2101A +48V +12V PWM ISL2100A ISL2101A SECONDARY CIRCUIT ISOLATION FIGURE 1. TWO-SWITCH FORWARD CONVERTER +48V +12V SECONDARY CIRCUIT PWM ISL2100A ISL2101A ISOLATION FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP 3 FN6294.0 June 8, 2006 ISL2100A, ISL2101A Absolute Maximum Ratings Supply Voltage, VDD, VHB - VHS (Notes 3, 4) . . . . . . . -0.3V to 18V LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on HO (Note 4) . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . 100mA Thermal Information Thermal Resistance (Typical) JA (C/W) JC (C/W) DFN (Note 5) . . . . . . . . . . . . . . . . . . . . 55 7.5 Max Power Dissipation at 25C in Free Air (DFN, Note 5) . . . . 2.27W Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65C to 150C Junction Temperature Range. . . . . . . . . . . . . . . . . . . -55C to 150C Lead Temperature (Soldering 10s - SOIC Lead Tips Only) . . 300C For Recommended soldering conditions see Tech Brief TB389. Maximum Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 14V Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V Voltage on HB . . VHS + 8V to VHS + 14V and VDD - 1V to VDD + 100V HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied. NOTES: 3. The ISL2100A-01A are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating curve for this mode of operation. 4. All voltages referenced to VSS unless otherwise specified. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. For JC, the "case temp" is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details. Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25C TJ = -40C to 125C MAX MIN MAX UNITS PARAMETERS SUPPLY CURRENTS VDD Quiescent Current VDD Quiescent Current VDD Operating Current VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent HB to VSS Current, Operating INPUT PINS Low Level Input Voltage Threshold Low Level Input Voltage Threshold High Level Input Voltage Threshold High Level Input Voltage Threshold Input Voltage Hysteresis Input Pull-down Resistance UNDER VOLTAGE PROTECTION VDD Rising Threshold VDD Threshold Hysteresis HB Rising Threshold HB Threshold Hysteresis SYMBOL TEST CONDITIONS MIN TYP IDD IDD IDDO IDDO IHB IHBO IHBS IHBSO ISL2100A; LI = HI = 0V ISL2101A; LI = HI = 0V ISL2100A; f = 500kHz ISL2101A; f = 500kHz LI = HI = 0V f = 500kHz LI = HI = 0V; VHB = VHS = 114V f = 500kHz; VHB = VHS = 114V - 0.1 0.3 1.6 1.9 0.1 2.0 0.05 0.9 0.25 0.45 2.2 2.5 0.15 2.5 1 - - 0.3 0.55 2.7 3 0.2 3 10 - mA mA mA mA mA mA A mA VIL VIL VIH VIH VIHYS RI ISL2100A ISL2101A ISL2100A ISL2101A ISL2100A 3.7 1.4 - 4.4 1.8 6.6 1.8 2.2 210 7.4 2.2 - 2.7 1.2 100 8.4 2.4 500 V V V V V k VDDR VDDH VHBR VHBH 6.8 6.2 - 7.3 0.6 6.9 0.6 7.8 7.5 - 6.5 5.9 - 8.1 7.8 - V V V V 4 FN6294.0 June 8, 2006 ISL2100A, ISL2101A Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued) TJ = 25C PARAMETERS BOOT STRAP DIODE Low Current Forward Voltage High Current Forward Voltage Dynamic Resistance LO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pull-Up Current Peak Pull-Down Current HO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pull-Up Current Peak Pull-Down Current VOLH VOHH IOHH IOLH IHO = 100mA IHO = -100mA, VOHH = VHB - VHO VHO = 0V VHO = 12V 0.25 0.25 2 2 0.3 0.3 0.4 0.4 V V A A VOLL VOHL IOHL IOLL ILO = 100mA ILO = -100mA, VOHL = VDD - VLO VLO = 0V VLO = 12V 0.25 0.25 2 2 0.3 0.3 0.4 0.4 V V A A VDL VDH RD IVDD-HB = 100A IVDD-HB = 100mA IVDD-HB = 100mA 0.5 0.7 0.8 0.6 0.9 1 0.7 1 1.5 V V SYMBOL TEST CONDITIONS MIN TYP MAX TJ = -40C to 125C MIN MAX UNITS Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25C MIN 1 1 CL = 1nF CL = 0.1F TYP 34 31 39 39 8 6 10 0.5 10 MAX 50 50 50 50 0.6 TJ = -40C to 125C MIN MAX 60 60 60 60 16 16 0.8 50 UNITS ns ns ns ns ns ns ns us ns ns PARAMETERS Lower Turn-Off Propagation Delay (LI Falling to LO Falling) Upper Turn-Off Propagation Delay (HI Falling to HO Falling) Lower Turn-On Propagation Delay (LI Rising to LO Rising) Upper Turn-On Propagation Delay (HI Rising to HO Rising) Delay Matching: Upper Turn-Off to Lower Turn-On Delay Matching: Lower Turn-Off to Upper Turn-On Either Output Rise/Fall Time (10% to 90%/90% to 10%) Either Output Rise/Fall Time (3V to 9V/9V to 3V) Minimum Input Pulse Width that Changes the Output Bootstrap Diode Turn-On or Turn-Off Time SYMBOL tLPHL tHPHL tLPLH tHPLH tMON tMOFF tRC,tFC tR,tF tPW tBS TEST CONDITIONS 5 FN6294.0 June 8, 2006 ISL2100A, ISL2101A Pin Descriptions SYMBOL VDD HB HO HS HI LI VSS LO EPAD DESCRIPTION Positive supply to lower gate driver. Bypass this pin to VSS. High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. High-side output. Connect to gate of high-side power MOSFET. High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. High-side input. Low-side input. Chip negative supply, which will generally be ground. Low-side output. Connect to gate of low-side power MOSFET. Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins. Timing Diagrams LI HI, LI tHPLH , tLPLH HO, LO tHPHL, tLPHL HI LO tMON HO tMOFF FIGURE 3. PROPAGATION DELAYS FIGURE 4. DELAY MATCHING Typical Performance Curves 10 10 IDDO (mA) 1 IDDO (mA) 1 .10 1 0.1 10 100 FREQUENCY (kHz) 3 0.1 10 100 FREQUENCY (kHz) 1 .10 3 T = -40C T = 25C T = 125C T = 150C T = -40C T = 25C T = 125C T = 150C FIGURE 5. ISL2100A IDD OPERATING CURRENT vs FREQUENCY FIGURE 6. ISL2101A IDD OPERATING CURRENT vs FREQUENCY 6 FN6294.0 June 8, 2006 ISL2100A, ISL2101A Typical Performance Curves 10 (Continued) 10 IHBO (mA) 1 IHBSO (mA) 1 .10 1 0.1 0.1 0.01 10 100 FREQUENCY (kHz) 3 0.01 10 100 FREQUENCY (kHz) 1 .10 3 T = -40C T= 25C T = 125C T = 150C T = -40C T = 25C T = 125C T = 150C FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY 500 450 VOHL, VOHH (mV) 450 400 VOLL, VOLH (mV) 400 350 300 250 200 150 50 0 50 TEMPERATURE (C) 100 150 350 300 250 200 150 50 0 50 TEMPERATURE (C) 100 150 VDD = VHB = 9V VDD = VHB = 12V VDD = VHB = 14V VDD = VHB = 9V VDD = VHB = 12V VDD = VHB = 14V FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE 7.6 0.6 VDDR, VHBR (V) 7.2 VDDH, VHBH (V) 7.4 0.55 0.5 7 0.45 6.8 50 0 50 TEMPERATURE (C) 100 150 0.4 50 0 50 TEMPERATURE (C) 100 150 VDDR VHBR VDDH VHBH FIGURE 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE FIGURE 12. UNDERVOLTAGE LOCKOUT HYSTERESIS vs TEMPERATURE 7 FN6294.0 June 8, 2006 ISL2100A, ISL2101A Typical Performance Curves tLPLH, tLPHL, tHPLH, tHPHL (ns) (Continued) 50 45 40 35 30 25 20 50 0 50 TEMPERATURE (C) 100 150 tLPLH, tLPHL, tHPLH, tHPHL (ns) 55 55 50 45 40 35 30 25 20 50 0 50 TEMPERATURE (C) 100 150 tLPLH tLPHL tHPLH tHPHL tLPLH tLPHL tHPLH tHPHL FIGURE 13. ISL2100A PROPAGATION DELAYS vs TEMPERATURE FIGURE 14. ISL2101A PROPAGATION DELAYS vs TEMPERATURE 10 9 tMON, tMOFF (ns) tMON, tMOFF (ns) 10 9 8 7 6 5 4 3 2 50 0 50 TEMPERATURE (C) 100 150 50 0 50 TEMPERATURE (C) 100 150 8 7 6 5 4 3 tMON tMOFF tMON tMOFF FIGURE 15. ISL2100A DELAY MATCHING vs TEMPERATURE FIGURE 16. ISL2101A DELAY MATCHING vs TEMPERATURE 2.5 2 IOHL, IOHH (A) 2.5 2 IOLL, IOLH (A) 1.5 1 0.5 0 1.5 1 0.5 0 0 2 4 6 VLO, VHO (V) 8 10 12 0 2 4 6 VLO, VHO (V) 8 10 12 FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE 8 FN6294.0 June 8, 2006 ISL2100A, ISL2101A Typical Performance Curves 260 240 220 200 180 160 140 120 100 80 60 40 20 0 (Continued) 0 5 10 VDD, VHB (V) 15 20 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 IDD, IHB (uA) IDD, IHB (uA) 0 5 10 VDD, VHB (V) 15 20 IDD IHB IDD IHB FIGURE 19. ISL2100A QUIESCENT CURRENT vs VOLTAGE FIGURE 20. ISL2101A QUIESCENT CURRENT vs VOLTAGE 1 FORWARD CURRENT (A) 120 VDD to VSS VOLTAGE (V) 0.1 0.01 3 1 .10 100 80 60 40 20 0 12 13 14 VHS to VSS VOLTAGE (V) 15 16 1 .10 1 .10 1 .10 4 5 6 0.3 0.4 0.5 0.6 FORWARD VOLTAGE (V) 0.7 0.8 FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE 9 FN6294.0 June 8, 2006 ISL2100A, ISL2101A Dual Flat No-Lead Plastic Package (DFN) 2X 0.15 C A A D 2X 0.15 C B L9.3x3 9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 E MIN 0.80 - NOMINAL 0.90 0.20 REF MAX 1.00 0.05 NOTES - A3 b D 0.20 5 INDEX AREA TOP VIEW B 0.25 3.00 BSC 0.30 4, 7 - D2 E // 0.10 C 0.08 C 1.85 2.00 3.00 BSC 2.10 6, 7 - E2 e k 0.80 0.95 0.50 BSC 1.05 6, 7 - A C SEATING PLANE SIDE VIEW A3 0.60 0.25 0.35 9 0.45 7 2 Rev. 0 3/06 L N D2 (DATUM B) 1 D2/2 2 6 7 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. All dimensions are in millimeters. Angles are in degrees. NX k E2 5 INDEX AREA (DATUM A) 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 6. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 7. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 8. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2. E2/2 NX L N 7 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 4 SECTION "C-C" CC e TERMINAL TIP (A1) 8L 4 0.10 M C A B FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6294.0 June 8, 2006 |
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